1. Field of the Invention
The embodiments described herein are directed to NAND memory devices, and more particularly to methods for fabricating smaller, higher density NAND memory devices.
2. Background of the Invention
NAND based flash memory has made possible a variety of new applications and storage capability. For example, NAND based memory was integral to removable media formats such as smart media, MMC, secured digital, memory sticks, and xD-picture cards. More recently, NAND based memory devices have been used for USB flash drives, MP3 players, digital cameras, and mobile phones, to name just a few newer applications. These new applications, however, constantly require smaller, higher density memory devices.
While multi level charge (MLC) techniques can be used to increase density and/or shrink the overall size of a NAND based memory device, the ability to use smaller, higher density devices is also dependent on the physical size constraints of each cell in the memory device. For example, one limitation on the cell size for conventional NAND based memory devices is the need for implanted bit lines in the memory array.
The inclusion of the implanted bit lines requires a certain area for each cell. If the need for the implanted bit lines is eliminated then the cell size can be reduced; however, conventional NAND based memory devices require the implanted bit lines. Accordingly, the reduction in size of conventional NAND based memory devices is limited.